NaNoINTEGRITY Defect Detection Technique to Capture Defects in SoC
System-on-chip (SoC) plays a key role in the success of smart products. With the rise in global demand for smart solutions, we are witnessing an acceleration in the need for rapid turnaround across SoC device miniaturization, feature implementation and rectification of manufacturing defects.
Chip manufacturers need a robust solution that would help them monitor, test, and deliver an integrated defect-free solution, ensuring faster time to market with an accurate offering.
LTTS proposes a novel NaNoINTEGRITY Defect Detection Technique to capture manufacturing defects in an SoC. The major benefit with this test technique stems from the reduced computational time in identifying a fault that can cause manufacturing defect in an SoC. LTTS’ NaNoINTEGRITY Defect Detection Technique captures the delay defects in a VLSI chip, leveraging the test flow to characterize the path speed and helping address speed binning challenges.
Businesses can also improve upon the classical ATPG approach of pattern generation utilized in any industrial ATPG tool, driving tremendous improvements to their SoC test quality.