We are hiring!
Are you a solution-driven game-changer who aspires to transform inspiration into innovation? And do you love engineering and technology?
If the answer to both these questions is yes, apply to LTTS Israel today.
LTTS Israel, based in Jerusalem, is home to a center of excellence for cyber-security and hosts a multi-member ASIC Hardware design facility. We are looking for exceptional professionals who have a passion for technology and innovation to join our expanding team.
It is your opportunity to be a part of one of the largest pure-play engineering services companies and cherish, nurture, and promote your engineering talents. After all, we are Engineer at
Why LTTS Israel?
- Core engineering expertise blended with an agile culture
- Next-generation center of cyber-security excellence and ASIC Hardware design
- LTTS University Program for driving career progression
- Our ASIC design facility in Israel provides a full range of services, including specifications, design, fabrication support, post-silicon services, and board design
- State-of-the-art security engineering for delivering world-class home and industrial network security
- Opportunity to collaborate with industry leaders
Hiring Design and Verification Engineers / Managers
ASIC Design Engineer
- Knowledge in Verilog/VHDL
- Experience in RTL blocks design, IPs integration, simulation and ASIC design flow
- Design quality checks (LINT, CDC)
- Basic knowledge in Structural Design (Synthesis, Timing closure, Formal Equivalence Check)
- Perl, TCL, Python scripting – an advantage
ASIC Verification Engineer / Team Lead
- Knowledge in pre silicon verification flow, from defining test plan, coverage plan, toward implementation of the verification environment.
- Building Verification environments, in System Verilog (UVM based)
- Debugging RTL using Mentor/Synopsys simulator.
- Programming skills in C (Assembly advantage), Perl, Verilog (Or VHDL).
- Understanding of chip architecture/design.
Failure Analysis Qualification Engineering
- Experience in HW Testing / Low Level coding
- Programming background Python, Pearl, VHDL, Verilog, C, C++.
- Experience with Test Equipment (logic analyzers and oscilloscopes)
- Familiar with Silicon production methods and testing (an advantage) and Assembly
- Familiar with Qualification testing
Post Silicon Group Manager
- Understand the Product Lifecycle's and various phases of validation from Simulation/Emulation to Post Silicon
- Understanding of the design production and testing of ASIC.
- Knowledge in test standards (JEDEC)
- FW Dev in C/C++ is an advantage
- Experience with the lab hardware equipment like DAQ, Logic Analyzer/O-scope/Emulators/FPGA cards and associated interfaces required to validate SoC
- Demonstrated skills for Project planning for post-silicon from Power On to PRQ and Post-launch Support