Error-Proofing SoC Design through Effective Post-Silicon Validation
In recent years, post-silicon validation and debugging has emerged as a major bottleneck in the design and manufacturing of system on chip (SoC). And it is not without reason. The process of post-silicon validation has several constraints that stem from the physical nature of the validation subject. The most prominent of these challenges is the limited scope of observing and controlling internal signals in manufactured chips. Additionally, manufacturers need to conduct post-silicon tests despite increasingly short time-to-market expectations. Given the demands for reliable devices and limited budgets, the answer to these challenges could very well lie in an effective post-silicon validation solution.
Effective Post-Silicon Validation Methodology
An effective post-silicon validation technique covers functional and timing behaviors, as well as other nonfunctional tests. This involves various tasks, such as validating the following aspects of the device: • Functional accuracy • Compatibility between hardware and firmware running on varied intellectual property (IP) cores • Power management • Performance validation • Security assurance • Tolerance for electrical noise margins • Ability to withstand thermal spikes and physical stress As it is practically impossible to completely remove a bug in the post-silicon validation phase, engineers need to localize the problem and identify its root cause before fixing the problem. Trace-based debugging techniques can help in quick resolution since they involve constant monitoring of the circuit’s behaviors during normal operations. Moreover, the use of on-chip buffers could improve observability and controllability of the internal signals during runtime. Extensive digital and analog simulations on high-capacity server farms are also instrumental in accelerating the silicon validation process. Simulation rates range anywhere between 10 to 10,000 cycles per second, depending on the type of simulation, design complexity, and tools used. For high-performance post-silicon validation, engineers could leverage simulation tools with multicore architecture. This would enhance operational efficiency and reduce waiting time, while allowing multiple tests to run simultaneously. With applications for SoCs growing rapidly across industries, manufacturers are better off refining their post-silicon validation processes sooner rather than later. Post-silicon testing solutions leveraging the latest innovations might just be the best bet for companies looking to improve product quality, stay within budget, and maximize profits by reducing time to market.